The present invention relates to a semiconductor memory cell including multiple transistors or a semiconductor memory cell including multiple transistors physically merged into one unit, and a method of manufacturing the above semiconductor memory cell.
As a high-density semiconductor memory cell, there has been made available a dynamic semiconductor memory cell that can be referred to as a single-transistor semiconductor memory cell including one transistor and one capacitor shown in FIG. 248. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, as the planar dimensions of the semiconductor memory cell are reduced, the capacitor formed in a parallel planar shape decreases in size, which causes a new problem that, when information which is stored as an electric charge in the capacitor of the semiconductor memory cell is read out, the read-out information is buried in noise, or that only a small voltage change is generated on the bit line since the stray capacitance of the bit line increases for every new generation of the semiconductor memory cell. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure shown in FIG. 249 or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or the groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to be suffered from the above mentioned limitation for the dimension beyond the low sub-micron rules unless expensive new materials are introduced for the capacitor.
In the planar dimensions smaller than those of the low sub-micron rule, the transistor constituting the semiconductor memory cell also has problems of deterioration of the drain breakdown voltage and drain-to-source punchthrough voltage. There is therefore a large risk that current leakage arises even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made smaller in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (Japanese Patent Laid-open No. 99251/1995), corresponding to U.S. Pat. No. 5,428,238. The semiconductor memory cell shown in FIGS. 15(A) and 15(B) of Japanese Patent Laid-Open No. 99251/1995 comprises a first semi-conductive region SC.sub.1 of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC.sub.2 formed in a surface region of the first semi-conductive region SC.sub.1 so as to form a rectifier junction together with the first semi-conductive region SC.sub.1, a second semi-conductive region SC.sub.3 of a second conductivity type formed in a surface region of the first semi-conductive region SC.sub.1 and spaced from the first conductive region SC.sub.2, a second conductive region SC.sub.4 formed in a surface region of the second semi-conductive region SC.sub.3 so as to form a rectifier junction together with the second semi-conductive region SC.sub.3, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC.sub.1 and the second conductive region SC.sub.4 and so as to bridge the first conductive region SC.sub.2 and the second semi-conductive region SC.sub.3, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC.sub.2 being connected to a write-in information setting line, and the second conductive region SC.sub.4 being connected to a second memory-cell-selecting line.
The first semi-conductive region SC.sub.1 (functioning as a channel forming region Ch.sub.2), the first conductive region SC.sub.2 (functioning as one source/drain region), the second semi-conductive region SC.sub.3 (functioning as the other source/drain region) and the conductive gate G constitute a switching transistor TR.sub.2. On the other hand, the second semi-conductive region SC.sub.3 (functioning as a channel forming region Ch.sub.1), the first semi-conductive region SC.sub.1 (functioning as one source/drain region), the second conductive region SC.sub.4 (functioning as the other source/drain region) and the conductive gate G constitute an information storing transistor TR.sub.1.
The semiconductor memory cell shown in FIGS. 12(A) and 13 of Japanese Patent Laid-Open No. 99251/1995 comprises a first conductive region SC.sub.1 of a first conductivity type formed in a p-type well (a fourth conductive region) SC.sub.4, a second conductive region SC.sub.2 formed in a surface region of the fourth conductive region SC.sub.4 so as to form a rectifier junction together with the fourth conductive region SC.sub.4, a third conductive region SC.sub.3 of a second conductivity type formed in a surface region of the first conductive region SC.sub.1 and spaced from the second conductive region SC.sub.2, and a conductive gate G formed on a barrier layer so as to bridge the first conductive region SC.sub.1 and the second conductive region SC.sub.2 and so as to bridge the third conductive region SC.sub.3 and the fourth conductive region SC.sub.4, the conductive gate G being connected to a first memory-cell-selecting line, the second conductive region SC.sub.2 being connected to a write-in information setting line, and the third conductive region SC.sub.3 being connected to a second memory-cell-selecting line. The third conductive region SC.sub.3 is constituted of a p-type semi-conductive region SC.sub.3p and a metal layer SC.sub.3s which is adjacent to the p-type semi-conductive region SC.sub.3p to form a Schottky junction. The regions SC.sub.3p and SC.sub.3s are formed in a surface region of the first conductive region SC.sub.1.
The first conductive region SC.sub.1 (functioning as a channel forming region Ch.sub.2), the fourth conductive region SC.sub.4 (functioning as one source/drain region), the third conductive region SC.sub.3 (functioning as the other source/drain region) and the conductive gate G constitute a switching transistor TR.sub.2. On the other hand, the fourth conductive region SC.sub.4 (functioning as a channel forming region Ch.sub.1), the first conductive region SC.sub.1 (functioning as one source/drain region), the second conductive region SC.sub.2 (functioning as the other source/drain region) and the conductive gate G constitute an information storing transistor TR.sub.1. The metal layer SC.sub.3s in itself does not constitute the source/drain region of the switching transistor TR.sub.2.
When information is written in the above semiconductor memory cells, the switching transistor TR.sub.2 is brought into an on-state. As a result, the information is stored in the channel forming region Ch.sub.1 of the information storing transistor TR.sub.1 as a potential or as an electric charge. When the information is read out, a threshold voltage of the information storing transistor TR.sub.1 seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch.sub.1 of the information storing transistor TR.sub.1. Therefore, when the information is read out, the storage state of the information storing transistor TR.sub.1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR.sub.1.
That is, in the semiconductor memory cell shown in FIGS. 15(A) and 15(B) of Japanese Patent Laid-Open No. 99251/1995, when the information is read out, the information storing transistor TR.sub.1 is brought into an on-state or an off-state, depending upon the information stored therein. Since the second conductive region SC.sub.4 is connected to the second memory-cell-selecting line, a large current or a small current may flow in the information storing transistor TR.sub.1, depending upon the stored information ("0" or "1"). In this way, the information stored in the semiconductor memory cell can be read out by utilizing the information storing transistor TR.sub.1. However, when the information is read out, the semiconductor memory cell has no mechanism for controlling the current which flows through the first semi-conductive region SC.sub.1 sandwiched by the first conductive region SC.sub.2 and the second semi-conductive region SC.sub.3. Therefore, when the information stored in the information storing transistor TR.sub.1 is detected with the conductive gate G, only a small margin of the current which flows between the first semi-conductive region SC.sub.1 and the second conductive region SC.sub.4 is obtained, which causes a problem that the number of the semiconductor memory cells connected to the second memory-cell-selecting line (a bit line) is limited.
Further, since the information storing transistor TR.sub.1 and the switching transistor TR.sub.2 are formed in the same main surface of the semiconductor substrate, the semiconductor memory cell has problems that it is large in size and that a margin in the manufacturing process of the semiconductor memory cell is small. The semiconductor memory cell may have a configuration in which the information storing transistor TR.sub.1 and the switching transistor TR.sub.2 are merged into one unit. As a result, the information storing transistor TR.sub.1 and the switching transistor TR.sub.2 may be formed in an area equivalent to that required for one conventional transistor. However, when the integration density of an integrated circuit is increased, the area of the integrated circuit increases proportional to the number of the semiconductor memory cells. As a result, it is difficult to fully satisfy the demand for manufacturing the semiconductor memory cell with a higher integration density.